1. Field of the Invention
The present invention pertains to the field of data transfer in a computer or other processing system. More particularly, the present invention pertains to obtaining coherent accesses to a target device when posted writes for the target device are used.
2. Description of Related Art
A posted write is a write cycle that is not immediately completed, but rather is stored in buffer circuitry for completion at a later time. Posting write cycles is often possible because data written to a storage location or a target device may not be needed immediately. Posting write cycles typically increases overall system efficiency because system resources may be used to perform cycles other than the write cycle. Thus, a new write posting technique may advantageously farther increase overall system efficiency.
One common prior art write posting technique is to use write buffers in a bus agent such as a microprocessor. The write buffers temporarily store write cycles that may otherwise be immediately generated by the bus agent. If such write buffers are used, the bus agent itself may redirect read cycles before write cycles posted in the write buffers so long as data coherency is maintained. Ensuring coherency typically involves ensuring that accesses to the same location are performed in the proper order so that stale data is not returned in the case of a read, and valid data is not over-written by a rescheduled write. Thus, read cycles are often redirected around write cycles as long as the read cycles are to different locations than the write cycles. Eventually, however, the write cycle must be executed under normal conditions.
Once the bus agent begins execution of the write cycle, certain portions of the bus agent may be unable to perform other tasks for an indeterminate amount of time until the target device can respond. Using conventional write cycle techniques, a write cycle may tie up bus agent resources in several manners. Some bus agents may be unable to perform other bus transactions until the write cycle completes. In this case, a slow target device prevents the bus agent from performing other bus transactions and therefore degrades performance.
Alternatively, a bus agent may utilize split transactions such that multiple bus transactions may be pending on the bus simultaneously. Even in this case, however, there is a limit on the number of bus transactions that may be simultaneously pending. Therefore, a slow write cycle ties up resources that could be used for other bus transactions. Additionally, in some cases, a bus agent may only allow one pending cycle for certain types of cycles such as input/output (I/O) cycles. In this case, a slow I/O cycle not only limits the number of other cycles which are simultaneously executed, but also completely prevents other I/O cycles from occurring until the slow I/O cycle is completed.
Accordingly, a technique which may free resources otherwise utilized throughout transactions involving high latency (i.e., slow) target devices may be advantageous. While semaphore techniques are often used to maintain memory coherency in memories accessed by multiple devices, such techniques may not have been employed in the prior art to improve the efficiency of bus transactions. Additionally, semaphore techniques may not have been employed in a particular interface hardware arrangement to maintain data coherency in particular types of bus transactions such as I/O transactions involving high latency I/O devices.
A method and apparatus that may be used to obtain coherent accesses with posted writes is disclosed. One method disclosed involves returning a semaphore indicator in an unlocked state and setting the semaphore indicator to a locked state in response to a semaphore indicator read when the semaphore indicator is in an unlocked state. A cycle for a target from a source is stored in an interface circuit, and the semaphore indicator is cleared to the unlocked state after the cycle completes to the target.